Design & Optimization of LDMOS Transistor Using Doped Silicon Pockets in Buried Oxide

Laterally Diffused MOSFET (LDMOS) devices are attractive devices for the new age flexible electronics applications. LDMOS devices offer various advantages over the conventional MOSFETS without much change in the fabrication flow. The primary force behind LDMOS is its huge volume use, which makes it possible for the technology to be continuously improved. The LDMOS device offers a higher breakdown voltage as compared to the conventional MOSFET devices, a characteristic of interest for the flexible electronics and other applications.

The current research work is aimed at studying the LDMOS device characteristics by way of modelling the device in a process simulator software package and to optimize the device to improve breakdown voltage and reduce the on-resistance. The research work involves a thorough modelling and optimization of the LDMOS device as per the fabrication sequences and studying the various performance metrics.